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| Categories | Nvidia AGX Xavier |
|---|---|
| Brand Name: | PLINK |
| Model Number: | Y-C8-DEV-Xavier |
| Place of Origin: | China |
| MOQ: | 1 |
| Price: | To be discussed |
| Payment Terms: | L/C, D/A, D/P, T/T |
| Supply Ability: | 1+set+4weeks |
| Delivery Time: | 15-30 work days |
| Packaging Details: | 195mm × 180mm × 50mm |
| NAME: | Industrial Embedded AGX Nvidia Xavier Jetson GPU Developer Kit 12V |
| Keyword: | Industrial Embedded AGX Nvidia Xavier Jetson GPU Developer Kit 12V |
| Memory: | 32GB 256-bit LPDDR4 x 136.5GB/s |
| Storage: | 32 GB eMMC 5.1 |
| USB: | *2 |
| Input Power: | DC +12V |
| Temperature Range: | -25℃ to 65℃ |
| GPIO(3.3V): | *1 |
| RS 232: | *2 |
| Networking: | 1 x 10/100/1000 Ethernet/RJ45 |
| Single Package Size: | 188mm × 170mm × 43mm |
Industrial Embedded AGX Nvidia Xavier Jetson GPU Developer Kit 12V
Jetson AGX Xavier GPU
NVIDIA Jetson AGX Xavier Developer Kit (Y-C8-DEV)
NVIDIA Jetson AGX Xavier Module (32G) + Y-C8 Carrier Board + Cooling FAN
The NVIDIA Jetson AGX Xavier module integrates a unified display controller (based on the NVIDIA NVDisplay architecture) and three independent display outputs. The Display Controller includes a Pixel Processing Engine that fetches pixel data to be processed from DRAM and generates up to six windows of rasterized display-ready pixel data. The instructions for processing the pixel data are captured by the display controller's Front End (FE) logic, which then generates the individual controls for the various stages of pixel processing. The pixel data to be processed are fetched in the Isochronous Memory Hub (IsoHub) then go through the specified pixel processing, including merging the cursor, in four pipe stages: Pre-Composition (Pre-comp); Composition (Comp); Post-Composition (Post-comp); and Raster Generation (RG). The rasterized display-ready pixel data are available for the separate panels/devices (referred to as display heads) and are fed through a multi-channel crossbar structure to the Serial Output Resources (SOR) in the Display Interface for the standard display output format, i.e. DP (Display Port) and HDMI (High Definition Multimedia Interface).
Each of the display heads can be run at an independent clock rate, and each can drive a different display resolution. Each of the six display windows (A, B, C, D, E, F) can be arbitrarily assigned to any of the display Heads as required, then connected to any one of the display heads for desired output format.
| CPU | 8-core NVIDIA Carmel Arm® v8.2 64-bit CPU 8MB L2 + 4MB L3 |
| GPU | 512-core NVIDIA Volta GPU with 64 Tensor Cores |
| USB Micro-B | 1 |
| USB Type-A | 1 |
| GPIO(3.3V) | 1 |
| SPI(3.3V) | 1 |
| I2C(3.3V) | 2 |
| RS 232 | 2 |
| Debug(UART) | 1 |
| CAN (with on-board transceiver) | 2 |
| Networking | 1 x 10/100/1000 Ethernet/RJ45 |
| Power Supply | DC +12V |
| Temperature | -25~+65°C |
| Size | 188mm × 170mm × 43mm |
| NVIDIA Jetson AGX Xavier Module | |
| AI Perf | 32 TOPS |
| GPU | 512-core NVIDIA Volta architecture GPU with 64 Tensor Cores |
| CPU | 8-core Arm® Cortex®-A78AE v8.2 64-bit CPU 2MB L2 + 4MB L3 |
| Memory | 32GB 256-bitLPDDR4x 136.5GB/s |
| Storage | 32GB eMMC 5.1 |
| CSI Camera | Up to 6 cameras (36 via virtual channels) 16 lanes MIPI CSI-2 | 8 lanes SLVS-EC D-PHY 1.2 (up to 40 Gbps) C-PHY 1.1 (up to 62 Gbps) |
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